You have 5+ years of experience in Verilog and SystemVerilog;familiarity with VHDL a plus.
Must be very experienced with Synopsys VCS, NC-Verilog, or Modelsim.
Strong scripting abilities in PERL are needed; TCL or Python is a plus.
Good communications skills are required and prior customer support experience is a plus.
Experience writing or maintaining the script or Makefile that builds the simulation Program from RTL is a plus. Familiarity with Verdi and / or DVE is considered a plus.
Knowledge at C and C++ is a plus.
You will Develop, maintain, and enhance an existing system for regressing RTL. Role involves debugging vendor tool problems.
Interacting with DV team to help solve their problems. Implement new functionality to solve emerging problems or to optimize already existing methods.
Education & Experience
BSc / MSc in Electrical Engineering or Computer Science.