We are looking for a bright student who will integrate into our FPGA design team.
The team is working on complicated IPs implementation using FPGAs and providing important tools for the CPU / SOC validation community.
The job includes working in a dynamic environment, understanding high speed protocols, mastering logic design using System Verilog and verification concepts as well as backend tools for synthesis and timing analysis.
BSC undergraduate student for Electrical Engineering with at least 4 semesters 'till graduation. Average of 80 or more. Ability to work independently.
Relevant courses (VLSI, Logic Design etc.) System Verilog / VHDL RTL programming language. SW knowledge