ASIC Engineer
F5 Networks
Tel Aviv
לפני 6 ימים

Come work at a place where innovation and teamwork come together to support the most exciting missions in the world!

Our Employees

Are valued and empowered, collaborative and team oriented, innovative in their approach and passionate about their work.

They are reliable, trustworthy and open with a high level of integrity. They value diversity, are inclusive and are committed to a global mindset

Position Summary :

Develop verification components in SystemVerilog UVM for complex designs. The DUT (Design Under Test) can be a block level module, where meticulousness is required.

Or integrated level that requires more of a system view.

Develop RTL modules in SystemVerilog. From module definition, through micro-architecture, coding and debug.

As a part of a small team, multitasking and flexibility is necessary. Tasks may change fast and more than one task is usually executed in parallel.

Attractions of the Job :

In this position, you will develop cutting edge FPGA designs. As a part of a small team, you will have a significant role.

You will have the opportunity to accelerate your design skills and responsibilities. We encourage initiative and even expect it.

Primary Responsibilities :

  • Write verification environment in UVM (60%)Define verification environment.Write UVM code.Write a test plan.Write functional coverage.
  • Run simulations.Debug simulation results including diving into HDL code.

  • RTL modules development (30%)Define design module.Create module micro-architecture.Write RTL code in SystemVerilog.Run simulation and debug.
  • Learn other skills and take responsibility (10%)Be proactive, always try to improve yourself and the team.Learn new methodologies and skills.
  • Other Responsibilities :

  • Responsible for upholding F5’s Business Code of Ethics and for promptly reporting violations of the Code or other company policies.
  • Performs other related duties as assigned.
  • Knowledge, Skills and Abilities :

  • Knowledge in UVM desirable.
  • Knowledge in SystemVerilog desirable.
  • Good communication skills. Ability to work as part of a team.
  • Self-learning. Ability to work independently.
  • Good English. Ability to communicate in English, both verbally and in writing is a must.
  • Qualifications :

  • 2-4 years of professional experience in design or verification.
  • BSEE or equivalent.
  • Physical Demands and Work Environment :

  • Duties are performed in a normal office environment while sitting at a desk or computer table. Duties require the ability to utilize a computer, communicate over the telephone, and read printed material.
  • Duties may require being on call periodically and working outside normal working hours (evenings).
  • Duties may require the ability to travel.
  • F5 Networks, is an equal opportunity employer and strongly supports diversity in the workplace.

    The Job Description is intended to be a general representation of the responsibilities and requirements of the job. However, the description may not be all-inclusive, and responsibilities and requirements are subject to change.

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