Come work at a place where innovation and teamwork come together to support the most exciting missions in the world!
Are valued and empowered, collaborative and team oriented, innovative in their approach and passionate about their work.
They are reliable, trustworthy and open with a high level of integrity. They value diversity, are inclusive and are committed to a global mindset
Position Summary :
Develop verification components in SystemVerilog UVM for complex designs. The DUT (Design Under Test) can be a block level module, where meticulousness is required.
Or integrated level that requires more of a system view.
Develop RTL modules in SystemVerilog. From module definition, through micro-architecture, coding and debug.
As a part of a small team, multitasking and flexibility is necessary. Tasks may change fast and more than one task is usually executed in parallel.
Attractions of the Job :
In this position, you will develop cutting edge FPGA designs. As a part of a small team, you will have a significant role.
You will have the opportunity to accelerate your design skills and responsibilities. We encourage initiative and even expect it.
Primary Responsibilities :
Run simulations.Debug simulation results including diving into HDL code.
Other Responsibilities :
Knowledge, Skills and Abilities :
Physical Demands and Work Environment :
F5 Networks, is an equal opportunity employer and strongly supports diversity in the workplace.
The Job Description is intended to be a general representation of the responsibilities and requirements of the job. However, the description may not be all-inclusive, and responsibilities and requirements are subject to change.